From 9bc3a97b269b2dcbb2656bcb74d4cbca637d19c4 Mon Sep 17 00:00:00 2001
From: Sam Anthony <sam@samanthony.xyz>
Date: Mon, 10 Nov 2025 18:20:28 -0500
Subject: use short register names

---
 fw/can.h    | 4 ++--
 fw/dac.h    | 8 ++++----
 fw/eeprom.h | 4 ++--
 fw/main.c   | 6 +++---
 fw/spi.c    | 6 +++---
 5 files changed, 14 insertions(+), 14 deletions(-)

(limited to 'fw')

diff --git a/fw/can.h b/fw/can.h
index 37c6bc7..d5c0db9 100644
--- a/fw/can.h
+++ b/fw/can.h
@@ -15,8 +15,8 @@
  */
 
 // Pin mapping
-#define CAN_CS_TRIS TRISAbits.TRISA5
-#define CAN_CS LATAbits.LATA5
+#define CAN_CS_TRIS TRISA5
+#define CAN_CS RA5
 
 // Bit timings (CNF1, CNF2, CNF3)
 #define CAN_TIMING_10K 0xDD, 0xAD, 0x06 // BRP=30, PropSeg=6, PS1=6, PS2=7, SP=65%, SJW=4
diff --git a/fw/dac.h b/fw/dac.h
index e9bf54b..3fec97a 100644
--- a/fw/dac.h
+++ b/fw/dac.h
@@ -12,10 +12,10 @@
  */
 
 // Pin mapping
-#define DAC1_CS_TRIS TRISBbits.TRISB7
-#define DAC1_CS LATBbits.LATB7
-#define DAC2_CS_TRIS TRISBbits.TRISB5
-#define DAC2_CS LATBbits.LATB5
+#define DAC1_CS_TRIS TRISB7
+#define DAC1_CS RB7
+#define DAC2_CS_TRIS TRISB5
+#define DAC2_CS RB5
 
 void dacInit(void);
 
diff --git a/fw/eeprom.h b/fw/eeprom.h
index 8d3d391..841b659 100644
--- a/fw/eeprom.h
+++ b/fw/eeprom.h
@@ -12,8 +12,8 @@
  */
 
 // Pin mapping
-#define EEPROM_CS_TRIS TRISCbits.TRISC5
-#define EEPROM_CS LATCbits.LATC5
+#define EEPROM_CS_TRIS TRISC5
+#define EEPROM_CS RC5
 
 typedef U16 EepromAddr;
 
diff --git a/fw/main.c b/fw/main.c
index c0e750e..499d0f0 100644
--- a/fw/main.c
+++ b/fw/main.c
@@ -114,8 +114,8 @@ loadSigFmts(void) {
 	Status status;
 
 	// Disable interrupts so the volatile address pointers can be passed safely
-	oldGie = INTCONbits.GIE;
-	INTCONbits.GIE = 0;
+	oldGie = GIE;
+	GIE = 0;
 
 	for (k = 0u; k < NSIG; k++) {
 		status = serReadSigFmt(sigFmtAddrs[k], (SigFmt *)&sigFmts[k]);
@@ -186,7 +186,7 @@ main(void) {
 
 	// Enable interrupts
 	INTCON = 0x00; // clear flags
-	OPTION_REGbits.INTEDG = 0; // interrupt on falling edge of INT pin
+	INTEDG = 0; // interrupt on falling edge of INT pin
 	INTE = 1; // enable INT pin
 	PEIE = 1; // enable peripheral interrupts
 	GIE = 1; // enable global interrupts
diff --git a/fw/spi.c b/fw/spi.c
index c8abe71..69bdec6 100644
--- a/fw/spi.c
+++ b/fw/spi.c
@@ -11,9 +11,9 @@ void
 spiInit(void) {
 	U8 junk;
 
-	TRISBbits.TRISB4 = IN; // SDI
-	TRISCbits.TRISC7 = OUT; // SDO
-	TRISBbits.TRISB6 = OUT; // SCK
+	TRISB4 = IN; // SDI
+	TRISC7 = OUT; // SDO
+	TRISB6 = OUT; // SCK
 
 	SSPSTAT = 0x40; // CKE=1
 	SSPCON1 = 0x22; // FOSC/64 => 750kHz SPI clock
-- 
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