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| author | Sam Anthony <sam@samanthony.xyz> | 2025-10-03 16:05:03 -0400 |
|---|---|---|
| committer | Sam Anthony <sam@samanthony.xyz> | 2025-10-03 16:05:03 -0400 |
| commit | 31937ab63b897b8092df64675a717a5b93d4d5dc (patch) | |
| tree | 7dfb64fdc168a8e99a92c86f6761361e17feaf88 /fw/can.h | |
| parent | e7baf2e96f1cec2071cb2e1e6a4735c36611bc26 (diff) | |
| download | can-gauge-interface-31937ab63b897b8092df64675a717a5b93d4d5dc.zip | |
CAN bit timing
Diffstat (limited to 'fw/can.h')
| -rw-r--r-- | fw/can.h | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/fw/can.h b/fw/can.h new file mode 100644 index 0000000..320c020 --- /dev/null +++ b/fw/can.h @@ -0,0 +1,26 @@ +/* Microchip MCP2515 CAN Controller + * + * Device: PIC16F1459 + * Compiler: XC8 v3.00 + * + * MCP2515 FOSC = 12MHz (48MHz/4 from PIC's CLKOUT) + * + * Usage: + * + * #include <stdint.h> + * #include "types.h" + * #include "can.h" + */ + +// Bit timings (CNF1, CNF2, CNF3) +#define CAN_TIMINGS_10K 0xDE, 0xAD, 0x06 // BRP=30, PropSeg=6, PS1=6, PS2=7, SP=65%, SJW=4 +#define CAN_TIMINGS_20K 0xCF, 0xAD, 0x06 // BRP=15, PropSeg=6, PS1=6, PS2=7, SP=65%, SJW=4 +#define CAN_TIMINGS_50K 0xC6, 0xAD, 0x06 // BRP=6, PropSeg=6, PS1=6, PS2=7, SP=65%, SJW=4 +#define CAN_TIMINGS_100K 0xC3, 0xAD, 0x06 // BRP=3, PropSeg=6, PS1=6, PS2=7, SP=65%, SJW=4 +#define CAN_TIMINGS_125K 0xC4, 0x9A, 0x03 // BRP=4, PropSeg=3, PS1=4, PS2=4, SP=66.7%, SJW=4 +#define CAN_TIMINGS_250K 0xC2, 0x9A, 0x03 // BRP=2, PropSeg=3, PS1=4, PS2=4, SP=66.7%, SJW=4 +#define CAN_TIMINGS_500K 0xC1, 0x9A, 0x03 // BRP=1, PropSeg=3, PS1=4, PS2=4, SP=66.7, SJW=4 +#define CAN_TIMINGS_800K "800kbps unsupported" // not possible with 12MHz clock +#define CAN_TIMINGS_1M "1Mbps unsupported" // not possible with 12MHz clock + +void canInit(void); |