tht quote

1 files changed, 2387 insertions, 0 deletions

diff --git a/hw/manufacturing/can_gauge_interface-B_Cu.gbr b/hw/manufacturing/can_gauge_interface-B_Cu.gbr
new file mode 100644
index 0000000..02e558c
--- /dev/null
+++ b/hw/manufacturing/can_gauge_interface-B_Cu.gbr
@@ -0,0 +1,2387 @@
+%TF.GenerationSoftware,KiCad,Pcbnew,9.0.0*%
+%TF.CreationDate,2025-09-27T10:55:46-04:00*%
+%TF.ProjectId,can_gauge_interface,63616e5f-6761-4756-9765-5f696e746572,0.1*%
+%TF.SameCoordinates,Original*%
+%TF.FileFunction,Copper,L4,Bot*%
+%TF.FilePolarity,Positive*%
+%FSLAX46Y46*%
+G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
+G04 Created by KiCad (PCBNEW 9.0.0) date 2025-09-27 10:55:46*
+%MOMM*%
+%LPD*%
+G01*
+G04 APERTURE LIST*
+G04 Aperture macros list*
+%AMRoundRect*
+0 Rectangle with rounded corners*
+0 $1 Rounding radius*
+0 $2 $3 $4 $5 $6 $7 $8 $9 X,Y pos of 4 corners*
+0 Add a 4 corners polygon primitive as box body*
+4,1,4,$2,$3,$4,$5,$6,$7,$8,$9,$2,$3,0*
+0 Add four circle primitives for the rounded corners*
+1,1,$1+$1,$2,$3*
+1,1,$1+$1,$4,$5*
+1,1,$1+$1,$6,$7*
+1,1,$1+$1,$8,$9*
+0 Add four rect primitives between the rounded corners*
+20,1,$1+$1,$2,$3,$4,$5,0*
+20,1,$1+$1,$4,$5,$6,$7,0*
+20,1,$1+$1,$6,$7,$8,$9,0*
+20,1,$1+$1,$8,$9,$2,$3,0*%
+G04 Aperture macros list end*
+%TA.AperFunction,ComponentPad*%
+%ADD10R,1.700000X1.700000*%
+%TD*%
+%TA.AperFunction,ComponentPad*%
+%ADD11O,1.700000X1.700000*%
+%TD*%
+%TA.AperFunction,ComponentPad*%
+%ADD12RoundRect,0.250000X-0.550000X0.550000X-0.550000X-0.550000X0.550000X-0.550000X0.550000X0.550000X0*%
+%TD*%
+%TA.AperFunction,ComponentPad*%
+%ADD13C,1.600000*%
+%TD*%
+%TA.AperFunction,ComponentPad*%
+%ADD14RoundRect,0.250000X-0.550000X-0.550000X0.550000X-0.550000X0.550000X0.550000X-0.550000X0.550000X0*%
+%TD*%
+%TA.AperFunction,ComponentPad*%
+%ADD15C,2.400000*%
+%TD*%
+%TA.AperFunction,ComponentPad*%
+%ADD16O,2.400000X2.400000*%
+%TD*%
+%TA.AperFunction,ComponentPad*%
+%ADD17O,3.200000X1.900000*%
+%TD*%
+%TA.AperFunction,ComponentPad*%
+%ADD18RoundRect,0.250001X1.599999X-1.099999X1.599999X1.099999X-1.599999X1.099999X-1.599999X-1.099999X0*%
+%TD*%
+%TA.AperFunction,ComponentPad*%
+%ADD19O,3.700000X2.700000*%
+%TD*%
+%TA.AperFunction,ComponentPad*%
+%ADD20C,1.700000*%
+%TD*%
+%TA.AperFunction,ComponentPad*%
+%ADD21C,3.500000*%
+%TD*%
+%TA.AperFunction,ComponentPad*%
+%ADD22RoundRect,0.250000X0.550000X0.550000X-0.550000X0.550000X-0.550000X-0.550000X0.550000X-0.550000X0*%
+%TD*%
+%TA.AperFunction,ViaPad*%
+%ADD23C,0.812800*%
+%TD*%
+%TA.AperFunction,Conductor*%
+%ADD24C,0.508000*%
+%TD*%
+%TA.AperFunction,Conductor*%
+%ADD25C,0.304800*%
+%TD*%
+G04 APERTURE END LIST*
+D10*
+%TO.P,JP5,1,A*%
+%TO.N,/CAN_L*%
+X55880000Y-134620000D03*
+D11*
+%TO.P,JP5,2,B*%
+%TO.N,Net-(JP5-B)*%
+X55880000Y-132080000D03*
+%TD*%
+D12*
+%TO.P,U8,1,Vdd*%
+%TO.N,+5VA*%
+X121920000Y-210820000D03*
+D13*
+%TO.P,U8,2,NC*%
+%TO.N,unconnected-(U8-NC-Pad2)*%
+X119380000Y-210820000D03*
+%TO.P,U8,3,~{CS}*%
+%TO.N,/DAC1_~{CS}*%
+X116840000Y-210820000D03*
+%TO.P,U8,4,SCK*%
+%TO.N,/SCK*%
+X114300000Y-210820000D03*
+%TO.P,U8,5,SDI*%
+%TO.N,/MOSI*%
+X111760000Y-210820000D03*
+%TO.P,U8,6,NC*%
+%TO.N,unconnected-(U8-NC-Pad6)*%
+X109220000Y-210820000D03*
+%TO.P,U8,7,NC*%
+%TO.N,unconnected-(U8-NC-Pad7)*%
+X106680000Y-210820000D03*
+%TO.P,U8,8,~{LDAC}*%
+%TO.N,GND*%
+X106680000Y-218440000D03*
+%TO.P,U8,9,~{SHDN}*%
+%TO.N,+5VA*%
+X109220000Y-218440000D03*
+%TO.P,U8,10,VB*%
+%TO.N,/AN2*%
+X111760000Y-218440000D03*
+%TO.P,U8,11,VrefB*%
+%TO.N,+5VA*%
+X114300000Y-218440000D03*
+%TO.P,U8,12,Vss*%
+%TO.N,GND*%
+X116840000Y-218440000D03*
+%TO.P,U8,13,VrefA*%
+%TO.N,+5VA*%
+X119380000Y-218440000D03*
+%TO.P,U8,14,VA*%
+%TO.N,/AN1*%
+X121920000Y-218440000D03*
+%TD*%
+%TO.P,C15,1*%
+%TO.N,GND*%
+X137160000Y-132080000D03*
+%TO.P,C15,2*%
+%TO.N,+5V*%
+X134660000Y-132080000D03*
+%TD*%
+D10*
+%TO.P,J6,1,Pin_1*%
+%TO.N,/CAN_~{CS}*%
+X111760000Y-134620000D03*
+%TD*%
+%TO.P,JP3,1,A*%
+%TO.N,VBUS*%
+X38100000Y-172720000D03*
+D11*
+%TO.P,JP3,2,B*%
+%TO.N,+5V*%
+X40640000Y-172720000D03*
+%TD*%
+D13*
+%TO.P,C13,1*%
+%TO.N,GND*%
+X93980000Y-127000000D03*
+%TO.P,C13,2*%
+%TO.N,+5V*%
+X96480000Y-127000000D03*
+%TD*%
+D10*
+%TO.P,J4,1,Pin_1*%
+%TO.N,/ICSP_~{MCLR}*%
+X162500000Y-86360000D03*
+D11*
+%TO.P,J4,2,Pin_2*%
+%TO.N,+5V*%
+X165040000Y-86360000D03*
+%TO.P,J4,3,Pin_3*%
+%TO.N,GND*%
+X167580000Y-86360000D03*
+%TO.P,J4,4,Pin_4*%
+%TO.N,/ICSP_DAT*%
+X170120000Y-86360000D03*
+%TO.P,J4,5,Pin_5*%
+%TO.N,/ICSP_CLK*%
+X172660000Y-86360000D03*
+%TD*%
+D13*
+%TO.P,C16,1*%
+%TO.N,+5VA*%
+X99060000Y-215940000D03*
+%TO.P,C16,2*%
+%TO.N,GND*%
+X99060000Y-218440000D03*
+%TD*%
+D10*
+%TO.P,JP2,1,A*%
+%TO.N,/INT*%
+X182880000Y-146035000D03*
+D11*
+%TO.P,JP2,2,C*%
+%TO.N,/INT{slash}ICSP_CLK*%
+X182880000Y-143495000D03*
+%TO.P,JP2,3,B*%
+%TO.N,/ICSP_CLK*%
+X182880000Y-140955000D03*
+%TD*%
+D10*
+%TO.P,JP1,1,A*%
+%TO.N,Net-(JP1-A)*%
+X157420000Y-99060000D03*
+D11*
+%TO.P,JP1,2,B*%
+%TO.N,/ICSP_~{MCLR}*%
+X154880000Y-99060000D03*
+%TD*%
+D13*
+%TO.P,C4,1*%
+%TO.N,Net-(U5-SW)*%
+X39255000Y-91585000D03*
+%TO.P,C4,2*%
+%TO.N,Net-(U5-BST)*%
+X41755000Y-91585000D03*
+%TD*%
+%TO.P,C12,1*%
+%TO.N,Net-(JP1-A)*%
+X165040000Y-99060000D03*
+%TO.P,C12,2*%
+%TO.N,GND*%
+X167540000Y-99060000D03*
+%TD*%
+D14*
+%TO.P,U4,1,~{CS}*%
+%TO.N,/ROM_~{CS}*%
+X127000000Y-137160000D03*
+D13*
+%TO.P,U4,2,MISO*%
+%TO.N,/MISO*%
+X127000000Y-139700000D03*
+%TO.P,U4,3,~{WP}*%
+%TO.N,+5V*%
+X127000000Y-142240000D03*
+%TO.P,U4,4,GND*%
+%TO.N,GND*%
+X127000000Y-144780000D03*
+%TO.P,U4,5,MOSI*%
+%TO.N,/MOSI*%
+X134620000Y-144780000D03*
+%TO.P,U4,6,SCK*%
+%TO.N,/SCK*%
+X134620000Y-142240000D03*
+%TO.P,U4,7,~{HOLD}*%
+%TO.N,+5V*%
+X134620000Y-139700000D03*
+%TO.P,U4,8,VCC*%
+X134620000Y-137160000D03*
+%TD*%
+D15*
+%TO.P,R10,1*%
+%TO.N,+5VA*%
+X132080000Y-204470000D03*
+D16*
+%TO.P,R10,2*%
+%TO.N,/DAC1_~{CS}*%
+X119380000Y-204470000D03*
+%TD*%
+D10*
+%TO.P,J8,1,Pin_1*%
+%TO.N,/DAC1_~{CS}*%
+X134620000Y-180340000D03*
+D11*
+%TO.P,J8,2,Pin_2*%
+%TO.N,/DAC2_~{CS}*%
+X134620000Y-177800000D03*
+%TD*%
+D13*
+%TO.P,C5,1*%
+%TO.N,GND*%
+X53245000Y-105555000D03*
+%TO.P,C5,2*%
+%TO.N,Net-(C5-Pad2)*%
+X55745000Y-105555000D03*
+%TD*%
+D17*
+%TO.P,SW1,1,1*%
+%TO.N,GND*%
+X134760000Y-93980000D03*
+X147260000Y-93980000D03*
+%TO.P,SW1,2,2*%
+%TO.N,/ICSP_~{MCLR}*%
+X134760000Y-98980000D03*
+X147260000Y-98980000D03*
+%TD*%
+D18*
+%TO.P,J3,1,Pin_1*%
+%TO.N,/AN1*%
+X37680000Y-210820000D03*
+D19*
+%TO.P,J3,2,Pin_2*%
+%TO.N,GND*%
+X37680000Y-206620000D03*
+%TO.P,J3,3,Pin_3*%
+%TO.N,/AN4*%
+X37680000Y-202420000D03*
+%TO.P,J3,4,Pin_4*%
+%TO.N,/AN2*%
+X43180000Y-210820000D03*
+%TO.P,J3,5,Pin_5*%
+%TO.N,GND*%
+X43180000Y-206620000D03*
+%TO.P,J3,6,Pin_6*%
+%TO.N,/AN3*%
+X43180000Y-202420000D03*
+%TD*%
+D15*
+%TO.P,R11,1*%
+%TO.N,+5VA*%
+X96520000Y-205740000D03*
+D16*
+%TO.P,R11,2*%
+%TO.N,/DAC2_~{CS}*%
+X96520000Y-193040000D03*
+%TD*%
+D18*
+%TO.P,J2,1,Pin_1*%
+%TO.N,/Tach*%
+X37680000Y-142140000D03*
+D19*
+%TO.P,J2,2,Pin_2*%
+%TO.N,GND*%
+X37680000Y-137940000D03*
+%TO.P,J2,3,Pin_3*%
+X37680000Y-133740000D03*
+%TO.P,J2,4,Pin_4*%
+%TO.N,+12V*%
+X37680000Y-129540000D03*
+%TO.P,J2,5,Pin_5*%
+%TO.N,/Speed*%
+X43180000Y-142140000D03*
+%TO.P,J2,6,Pin_6*%
+%TO.N,/CAN_H*%
+X43180000Y-137940000D03*
+%TO.P,J2,7,Pin_7*%
+%TO.N,/CAN_L*%
+X43180000Y-133740000D03*
+%TO.P,J2,8,Pin_8*%
+%TO.N,GND*%
+X43180000Y-129540000D03*
+%TD*%
+D13*
+%TO.P,C14,1*%
+%TO.N,GND*%
+X78740000Y-135890000D03*
+%TO.P,C14,2*%
+%TO.N,+5V*%
+X78740000Y-133390000D03*
+%TD*%
+D12*
+%TO.P,U9,1,Vdd*%
+%TO.N,+5VA*%
+X93980000Y-210820000D03*
+D13*
+%TO.P,U9,2,NC*%
+%TO.N,unconnected-(U9-NC-Pad2)*%
+X91440000Y-210820000D03*
+%TO.P,U9,3,~{CS}*%
+%TO.N,/DAC2_~{CS}*%
+X88900000Y-210820000D03*
+%TO.P,U9,4,SCK*%
+%TO.N,/SCK*%
+X86360000Y-210820000D03*
+%TO.P,U9,5,SDI*%
+%TO.N,/MOSI*%
+X83820000Y-210820000D03*
+%TO.P,U9,6,NC*%
+%TO.N,unconnected-(U9-NC-Pad6)*%
+X81280000Y-210820000D03*
+%TO.P,U9,7,NC*%
+%TO.N,unconnected-(U9-NC-Pad7)*%
+X78740000Y-210820000D03*
+%TO.P,U9,8,~{LDAC}*%
+%TO.N,GND*%
+X78740000Y-218440000D03*
+%TO.P,U9,9,~{SHDN}*%
+%TO.N,+5VA*%
+X81280000Y-218440000D03*
+%TO.P,U9,10,VB*%
+%TO.N,/AN4*%
+X83820000Y-218440000D03*
+%TO.P,U9,11,VrefB*%
+%TO.N,+5VA*%
+X86360000Y-218440000D03*
+%TO.P,U9,12,Vss*%
+%TO.N,GND*%
+X88900000Y-218440000D03*
+%TO.P,U9,13,VrefA*%
+%TO.N,+5VA*%
+X91440000Y-218440000D03*
+%TO.P,U9,14,VA*%
+%TO.N,/AN3*%
+X93980000Y-218440000D03*
+%TD*%
+D10*
+%TO.P,J1,1,VBUS*%
+%TO.N,VBUS*%
+X38735000Y-159980000D03*
+D20*
+%TO.P,J1,2,D-*%
+%TO.N,/USB_D-*%
+X38735000Y-157480000D03*
+%TO.P,J1,3,D+*%
+%TO.N,/USB_D+*%
+X36735000Y-157480000D03*
+%TO.P,J1,4,GND*%
+%TO.N,GND*%
+X36735000Y-159980000D03*
+D21*
+%TO.P,J1,5,Shield*%
+%TO.N,unconnected-(J1-Shield-Pad5)*%
+X34025000Y-164750000D03*
+%TO.N,unconnected-(J1-Shield-Pad5)_1*%
+X34025000Y-152710000D03*
+%TD*%
+D10*
+%TO.P,J9,1,Pin_1*%
+%TO.N,+12V*%
+X71120000Y-106680000D03*
+D11*
+%TO.P,J9,2,Pin_2*%
+%TO.N,+6.5V*%
+X73660000Y-106680000D03*
+%TO.P,J9,3,Pin_3*%
+%TO.N,+5V*%
+X76200000Y-106680000D03*
+%TO.P,J9,4,Pin_4*%
+%TO.N,GND*%
+X78740000Y-106680000D03*
+%TD*%
+D10*
+%TO.P,JP4,1,A*%
+%TO.N,VBUS*%
+X48260000Y-172720000D03*
+D11*
+%TO.P,JP4,2,B*%
+%TO.N,+5VA*%
+X50800000Y-172720000D03*
+%TD*%
+D14*
+%TO.P,U1,1,VDD*%
+%TO.N,+5V*%
+X162560000Y-127000000D03*
+D13*
+%TO.P,U1,2,RA5/SOSCI/T1CKI/OSC1/CLKIN*%
+%TO.N,/DAC2_~{CS}*%
+X162560000Y-129540000D03*
+%TO.P,U1,3,RA4/AN3/SOSCO/T1G/OSC2/CLKOUT/CLKR*%
+%TO.N,/CLK*%
+X162560000Y-132080000D03*
+%TO.P,U1,4,RA3/T1G/~{SS}/~{MCLR}/Vpp*%
+%TO.N,/~{MCLR}*%
+X162560000Y-134620000D03*
+%TO.P,U1,5,PWM1/CWG1A/T0CKI/RC5*%
+%TO.N,unconnected-(U1-PWM1{slash}CWG1A{slash}T0CKI{slash}RC5-Pad5)*%
+X162560000Y-137160000D03*
+%TO.P,U1,6,CWG1B/C1OUT/C2OUT/RC4*%
+%TO.N,/Speed*%
+X162560000Y-139700000D03*
+%TO.P,U1,7,CLKR/C1IN3-/C2IN3-/DACOUT2/AN7/RC3*%
+%TO.N,/Tach*%
+X162560000Y-142240000D03*
+%TO.P,U1,8,~{SS}/PWM2/AN8/RC6*%
+%TO.N,/CAN_~{CS}*%
+X162560000Y-144780000D03*
+%TO.P,U1,9,SDO/AN9/RC7*%
+%TO.N,/MOSI*%
+X162560000Y-147320000D03*
+%TO.P,U1,10,RB7/TX/CK*%
+%TO.N,/DAC1_~{CS}*%
+X162560000Y-149860000D03*
+%TO.P,U1,11,RB6/SCL/SCK*%
+%TO.N,/SCK*%
+X170180000Y-149860000D03*
+%TO.P,U1,12,RB5/AN11/RX/DX*%
+%TO.N,/ROM_~{CS}*%
+X170180000Y-147320000D03*
+%TO.P,U1,13,RB4/AN10/SDA/SDI*%
+%TO.N,/MISO*%
+X170180000Y-144780000D03*
+%TO.P,U1,14,C2IN2-/C1IN2-/DACOUT1/AN6/RC2*%
+%TO.N,unconnected-(U1-C2IN2-{slash}C1IN2-{slash}DACOUT1{slash}AN6{slash}RC2-Pad14)*%
+X170180000Y-142240000D03*
+%TO.P,U1,15,ICSPCLK/~{CWGFLT}/C2IN-/C1IN-/AN5/RC1*%
+%TO.N,/INT{slash}ICSP_CLK*%
+X170180000Y-139700000D03*
+%TO.P,U1,16,ICSPDAT/C2IN+/C1IN+/Vref+/AN4/RC0*%
+%TO.N,/ICSP_DAT*%
+X170180000Y-137160000D03*
+%TO.P,U1,17,Vusb3v3*%
+%TO.N,Net-(U1-Vusb3v3)*%
+X170180000Y-134620000D03*
+%TO.P,U1,18,RA1/D-/ICSPCLK*%
+%TO.N,/USB_D-*%
+X170180000Y-132080000D03*
+%TO.P,U1,19,RA0/D+/ICSPDAT*%
+%TO.N,/USB_D+*%
+X170180000Y-129540000D03*
+%TO.P,U1,20,VSS*%
+%TO.N,GND*%
+X170180000Y-127000000D03*
+%TD*%
+D15*
+%TO.P,R9,1*%
+%TO.N,+5V*%
+X134620000Y-127000000D03*
+D16*
+%TO.P,R9,2*%
+%TO.N,/ROM_~{CS}*%
+X121920000Y-127000000D03*
+%TD*%
+D14*
+%TO.P,U2,1,TXCAN*%
+%TO.N,/CAN_TX*%
+X88900000Y-132080000D03*
+D13*
+%TO.P,U2,2,RXCAN*%
+%TO.N,/CAN_RX*%
+X88900000Y-134620000D03*
+%TO.P,U2,3,CLKOUT/SOF*%
+%TO.N,unconnected-(U2-CLKOUT{slash}SOF-Pad3)*%
+X88900000Y-137160000D03*
+%TO.P,U2,4,~{TX0RTS}*%
+%TO.N,+5V*%
+X88900000Y-139700000D03*
+%TO.P,U2,5,~{TX1RTS}*%
+X88900000Y-142240000D03*
+%TO.P,U2,6,~{TX2RTS}*%
+X88900000Y-144780000D03*
+%TO.P,U2,7,OSC2*%
+%TO.N,unconnected-(U2-OSC2-Pad7)*%
+X88900000Y-147320000D03*
+%TO.P,U2,8,OSC1*%
+%TO.N,/CLK*%
+X88900000Y-149860000D03*
+%TO.P,U2,9,VSS*%
+%TO.N,GND*%
+X88900000Y-152400000D03*
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